1) Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having chip information indicating a revision history.
2) Description of the Related Art
Generally, revision of logic and a layout is performed for several times during development and manufacturing of a semiconductor chip for a purpose of correcting the logic or improving quality of the semiconductor chip. Information on a history of the revision is kept by a manufacturer of the semiconductor chip, and chip information that indicates a version number is stored in the semiconductor chip. By reading the chip information from the semiconductor chip and by checking the chip information against the history of the revision, it is possible for a user and the manufacturer to learn a revision history of the semiconductor chip.
Conventionally, the chip information is stored in a memory such as a read-only memory (ROM) in a chip. Therefore, when the chip information is required, the chip information is read from the memory. Several bits data that is formed with “0” or “1” is formed using a part of a specific wiring layer, for example, a first wiring layer, in a multilayer wiring structure that forms the memory. In other words, for example, a wiring for several bits to store the chip information is arranged in the first wring layer so that the wiring outputs the data of “0” or “1” that is predetermined as the chip information.
A wiring pattern for the wiring to store the chip information is determined based on a mask pattern used to form the wiring in the first wiring layer on a surface of a semiconductor during a process of manufacturing the semiconductor chip. Therefore, when the revision is performed, it is necessary to change the mask pattern because a new piece of the chip information is to be stored in the memory.
An apparatus in which an output value of the apparatus is changeable between “0” and “1” just by changing a wiring in a single layer is disclosed in, for example, Japanese Patent Application Laid-Open No. H8-181068. The apparatus includes two input terminals and two output terminals. “0” is input into one of the input terminals, and “1” is input into another of the input terminals, and “0” is output from one of the output terminals, and “1” is output from another of the output terminals. In the apparatus, N pieces of programmable cells that reverse outputs of the two output units by changing an internal wiring are formed corresponding to a 1-N layer, and are connected in series.
In the above conventional technology, it is possible to perform the revisions to change the wiring pattern to revise the logic and to improve the quality, and the revisions to change the wiring pattern for updating the chip information at a same time if the wirings of which the wiring pattern is to be revised are in a same wiring layer (for example, in the first wiring layer). In other words, in this case, it is only necessary to change the mask pattern to form the wiring of the first wiring layer.
However, a wiring layer in which the wiring to store the chip information is fixed, for example, to the first wiring layer, when a wiring layer of which the wiring pattern is to be revised to revise the logic and to improve the quality is not the first wiring layer, it becomes necessary to change the mask pattern of both the wiring layers. Therefore, a number of the mask pattern to be changed at a version revision increases by one, resulting increase of a manufacturing cost. A “mask” includes a “reticle” that is used when projection by a lithography that is called “stepper” is repeated while shifting a position to be projected on a whole surface of a wafer.